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 HAT3018R, HAT3018RJ
Silicon N/P Channel Power MOS FET High Speed Power Switching
REJ03G0127-0100Z Rev.1.00 Oct.20.2003
Features
* * * * Low on-resistance Capable of 4.5 V gate drive High density mounting "J" is for Automotive application High temperature D-S leakage guarantee Avalanche rating
Outline
SOP-8
8 5 76
3 12 78 DD 56 DD
4
2 G
4 G
S1
S3
1, 3 Source 2, 4 Gate 5, 6, 7, 8 Drain
MOS1 Nch
MOS2 Pch
Rev.1.00, Oct.20.2003, page 1 of 15
HAT3018R, HAT3018RJ
Absolute Maximum Ratings
(Ta = 25C)
Ratings Item Symbol HAT3018R Nch Drain to source voltage Gate to source voltage Drain current Drain peak current Avalanche current Avalanche energy Channel dissipation Channel dissipation Channel temperature Storage temperature Notes: 1. 2. 3. 4. VDSS VGSS ID ID (pulse) IAP
Note4 Note1
HAT3018RJ Pch -60 20 -5 -40 -- -- 2 3 150 Nch 60 20 6 48 6 3.08 2 3 150 Pch -60 20 -5 -40 -5 2.14 2 3 150
Unit
60 20 6 48 -- -- 2 3 150
V V A A A mJ W W C
EARNote4 Pch
Note2
PchNote3 Tch Tstg
-55 to +150 -55 to +150 -55 to +150 -55 to +150 C
PW 10s, duty cycle 1% 1 Drive operation: When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW 10 s 2 Drive operation: When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW 10 s Value at Tch = 25C, Rg 50
Rev.1.00, Oct.20.2003, page 2 of 15
HAT3018R, HAT3018RJ
Electrical Characteristics
* N Channel (Ta = 25C)
Item Drain to source breakdown voltage Symbol Min V(BR)DSS 60 Typ -- -- -- -- -- -- -- 9.5 28 40 1000 145 85 15 2 3 12 10 60 11 0.82 40 Max -- -- 1 -- 10 10 2.5 -- 35 50 -- -- -- -- -- -- -- -- -- -- 1.07 -- Unit V V A A A A V S m m pF pF pF nC nC nC ns ns ns ns V ns VDD = 25 V VGS = 10 V ID = 6 A VGS = 10 V, ID= 3 A VDD 30 V RL = 10 RG = 4.7 IF = 6 A, VGS = 0
Note 5
Test Conditions ID = 10 mA, VGS = 0 IG = 100 A, VDS = 0 VDS = 60 V, VGS = 0 VDS = 48 V, VGS = 0 Ta = 125C VGS = 16 V, VDS = 0 VDS = 10 V, ID = 1 mA ID = 3 ANote 5, VDS = 10 V ID = 3 ANote 5, VGS = 10 V ID = 3 ANote 5, VGS = 4.5 V VDS = 10 V, VGS = 0 f = 1 MHz
Gate to Source breakdown voltage V(BR)GSS 20 Zero gate voltage drain current Zero gate voltage drain current HAT3018R IDSS IDSS IGSS VGS(off) |yfs| RDS(on) RDS(on) Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDF -- -- -- -- 1.5 6 -- -- -- -- -- -- -- -- -- -- -- -- -- --
HAT3018RJ IDSS
Gate to source leak current Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage
Body-drain diode reverse recovery trr time Notes: 5. Pulse test
IF = 6 A, VGS = 0 diF/dt = 100A/ s
Rev.1.00, Oct.20.2003, page 3 of 15
HAT3018R, HAT3018RJ * P Channel (Ta = 25C)
Item Drain to source breakdown voltage Gate to Source breakdown voltage Zero gate voltage drain current Zero gate voltage drain current HAT3018R Symbol V(BR)DSS V(BR)GSS IDSS IDSS IGSS VGS(off) |yfs| RDS(on) RDS(on) Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf Min -60 20 -- -- -- -- -1.0 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- 5 60 90 1350 135 85 21 3 4 20 15 55 10 -0.85 25 Max -- -- -1 -- -10 10 -2.5 -- 76 130 -- -- -- -- -- -- -- -- -- -- -1.10 -- Unit V V A A A A V S m m pF pF pF nC nC nC ns ns ns ns V ns VDD = -25 V VGS = -10 V ID = -5 A VGS = -10 V, ID= -2.5 A VDD -30 V RL = 12 RG = 4.7 IF = -5 A, VGS = 0Note 5 IF = -5 A, VGS = 0 diF/dt = 100A/ s Test Conditions ID = -10 mA, VGS = 0 IG = 100 A, VDS = 0 VDS = -60 V, VGS = 0 VDS = -48 V, VGS = 0 Ta = 125C VGS = 16 V, VDS = 0 VDS = -10 V, ID = 1 mA ID = -2.5 ANote 5, VDS = -10 V ID = -2.5 ANote 5, VGS = -10 V ID = -2.5 ANote 5, VGS = -4.5V VDS = -10 V, VGS = 0 f = 1 MHz
HAT3018RJ IDSS
Gate to source leak current Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time
Body-drain diode forward voltage VDF Body-drain diode reverse recovery time Notes: 5. Pulse test trr
Rev.1.00, Oct.20.2003, page 4 of 15
HAT3018R, HAT3018RJ
Main Characteristics
* N Channel
Maximum Safe Operation Area 10
10
PW
100 30
(A)
Typical Output Characteristics
s
(A)
10 10 V 4V 8 Pulse Test
10 3 1 0.3
DC Op era tio
Drain Current ID
s
Drain Current ID
=1
1m
s
0 s
0m
6 3V 4
n(
0.1 Operation in
this area is 0.03 limited by RDS(on)
PW
< 1 ote 6 0s )
N
0.01 Ta = 25C 0.003 1 shot Pulse 1 Drive Operation 0.001 0.1 0.3 1 3 10 30 100 Drain to Source Voltage VDS (V) Note 6: When using the glass epoxy board (FR4 40 x 40 x 1.6 mm)
2 VGS= 2.5 V 0 2 4 6 Drain to Source voltage 8 10 VDS (V)
Typical Transfer Characteristics
Drain to Source Saturation Voltage VDS(on) (V)
Drain to Source Saturation Voltage vs. Gate to Source Voltage 0.3 Pulse Test
10 VDS = 10 V Pulse Test
(A)
8
Drain Current ID
0.2 ID = 5 A 0.1 2A 1A 20 15 5 10 Gate to Source Voltage VGS (V)
6
4 Tc = 75C 2 -25C 0 1 2 3 Gate to Source Voltage 4 5 VGS (V) 25C
0
Rev.1.00, Oct.20.2003, page 5 of 15
HAT3018R, HAT3018RJ
Drain to Source on State Resistance RDS(on) ()
Pulse Test 0.5 0.2 0.1 0.05 VGS = 4.5 V 10 V
Drain to Source on State Resistance RDS(on) ()
Static Drain to Source on State Resistance vs. Drain Current 1.0
Static Drain to Source on State Resistance vs. Temperature 0.10 Pulse Test 0.08 1, 2 ,5A
0.06 VGS = 4.5 V 0.04 1, 2, 5 A 0.02 0 -40 10 V
0.02 0.01 1
3
10
30
100
0
40
80 Tc
120 (C)
160
Drain Current ID (A)
Case Temperature
Forward Transfer Admittance vs. Drain Current
Forward Transfer Admittance |yfs| (S)
Body-Drain Diode Reverse Recovery Time 1000
Reverse Recovery Time trr (ns)
50 20 10 5 2 1 0.5 0.1 VDS = 10 V Pulse Test 0.3 1 3 10 30 Drain Current ID (A) 100 Tc = -25C 25C 75C
500
di / dt = 100 A / s VGS = 0, Ta = 25C
200 100 50
20 10 0.1
0.3
1
3
10
30 IDR (A)
100
Reverse Drain Current
Rev.1.00, Oct.20.2003, page 6 of 15
HAT3018R, HAT3018RJ
Typical Capacitance vs. Drain to Source Voltage
5000 2000
100
Dynamic Input Characteristics ID = 6 A VGS
20 16 12 8 4 0 40
VDS (V)
Capacitance C (pF)
1000 500 200 100 50 20 10 0 VGS = 0 f = 1 MHz 10 20 30 40 Drain to Source Voltage VDS
Drain to Source Voltage
Coss Crss
40 20
VDD = 50 V 25 V 10 V 8 16 24 32 Gate Charge Qg (nc)
50 (V)
0
Reverse Drain Current vs. Source to Drain Voltage 20
(A)
Reverse Drain Current IDR
16 10 V 12 8 4 0 5V
Pulse Test
VGS = 0, -5 V
0.4 0.8 1.2 Source to Drain Voltage
1.6 VSD
2.0 (V)
Rev.1.00, Oct.20.2003, page 7 of 15
Gate to Source Voltage
Ciss
80 V = 50 V DD 25 V 10 V 60 VDS
VGS (V)
HAT3018R, HAT3018RJ
Maximum Avalanche Energy vs. Channel Temperature Derating
Repetitive Avalanche Energy EAR (mJ)
Switching Characteristics 1000 300
Switching Time t (ns)
4.0 IAP = 6 A VDD = 25 V L = 100 H duty < 0.1 % Rg > 50
3.2
100 td(off) 30 10 3 1 0.1 tr td(on) tf VGS = 10 V, VDD = 30 V PW = 5 s, duty < 1 % 0.3 1 3 Drain Current 10 30 ID (A) 100
2.4
1.6
0.8 0 25
50 75 100 125 150 Channel Temperature Tch (C)
Switching Time Test Circuit Vout Monitor D.U.T. RL Vout Vin 10 V V DS = 30V td(on) Vin
Switching Time Waveform 90% 10% 10% 90% tr 90% td(off) tf 10%
Vin Monitor Rg
Avalanche Test Circuit EAR =
Avalanche Waveform 1 2 * L * I AP * 2 VDSS VDSS - V DD
V DS Monitor
L I AP Monitor
V (BR)DSS I AP VDD ID V DS
Rg Vin 15 V
D. U. T
50 0 VDD
Rev.1.00, Oct.20.2003, page 8 of 15
HAT3018R, HAT3018RJ * P Channel
Maximum Safe Operation Area 10
10
PW =1
Typical Output Characteristics
s
-100 -30
(A)
-10 -10 V
(A)
Pulse Test
-10 -3 -1 -0.3
DC Op era
1m
0
s
s
s
-8
Drain Current ID
Drain Current ID
0m
-6 V -4.5 V
-3.5 V
-6
tio
-0.1 Operation in this area is -0.03 limited by RDS(on)
n(
PW
< 1 ote 6 0s )
N
-4
-0.01 Ta = 25C -0.003 1 shot Pulse 1 Drive Operation -0.001 -0.1 -0.3 -1 -3 -10 -30 -100 Drain to Source Voltage VDS (V) Note 6: When using the glass epoxy board (FR4 40 x 40 x 1.6 mm)
-2 VGS = -2.5 V 0 -2 -4 -6 Drain to Source Voltage -8 VDS (V) -10
Typical Transfer Characteristics
Drain to Source Saturation Voltage VDS(on) (V)
Drain to Source Saturation Voltage vs. Gate to Source Voltage -1 Pulse Test -0.8
-10 VDS = -10 V Pulse Test
(A) Drain Current ID
-8
-6
-0.6
-4
-0.4 ID = -5 A -0.2 0 0 -2 A -1 A -4 -8 -12 -16 VGS (V) -20
-2 Tc = 75C 0 -1 -2 25C -25C -3 -4 VGS (V) -5
Gate to Source Voltage
Gate to Source Voltage
Rev.1.00, Oct.20.2003, page 9 of 15
HAT3018R, HAT3018RJ
Drain to Source on State Resistance RDS(on) ()
0.5 0.2 0.1 0.05 VGS = -4.5 V
Drain to Source on State Resistance RDS(on) ()
Static Drain to Source on State Resistance vs. Drain Current 1.0 Pulse Test
Static Drain to Source on State Resistance vs. Temperature 0.25 Pulse Test 0.20 -5 A 0.15 VGS = -4.5 V 0.10 -5 A -1, -2 A ID = -1, -2 A
-10 V
0.02 0.01 -1
0.05 0 -40
-10 V 0 40 80
-3
-10
-30
-100
120 Tc (C)
160
Drain Current ID (A)
Case Temperature
Forward Transfer Admittance |yfs| (S)
50 20 10 5 2 1
Forward Transfer Admittance vs. Drain Current
Body-Drain Diode Reverse Recovery Time 1000
Reverse Recovery Time trr (ns)
500
di / dt = 100 A / s VGS = 0, Ta = 25C
200 100 50
Tc = -25C 25C 75C
VDS = -10 V Pulse Test -1 -3 -10 -30 -100
20 10 -0.1 -0.3
0.5 -0.1 -0.3
-1
-3
-10
-30 IDR (A)
-100
Drain Current ID (A)
Reverse Drain Current
Rev.1.00, Oct.20.2003, page 10 of 15
HAT3018R, HAT3018RJ
Typical Capacitance vs. Drain to Source Voltage
Dynamic Input Characteristics
VDS (V)
5000 2000
0
Capacitance C (pF)
-20
-4 ID = -5 A
1000 500 200 100 50 Crss 20 10 0 VGS = 0 f = 1 MHz -10 -20 -30 -40 -50 (V) Coss Ciss
Drain to Source Voltage
-40 VDS -60 VDD = -10 V -25 V -50 V VGS
-8
-12
-80
-16 -20 40
-100
0
8
16
24
32
Drain to Source Voltage VDS
Gate Charge
Qg (nc)
Reverse Drain Current vs. Source to Drain Voltage -10
(A)
Pulse Test -8 -10 V -6 -5 V VGS = 0, 5 V
Reverse Drain Current IDR
-4
-2 0 0
-0.4 -0.8 -1.2 Source to Drain Voltage
-1.6 -2.0 VSD (V)
Rev.1.00, Oct.20.2003, page 11 of 15
Gate to Source Voltage
VGS (V)
VDD = -10 V -25 V -50 V
0
HAT3018R, HAT3018RJ
Switching Characteristics 1000 300 100 30 10 3 1 -0.1 -0.3 tf VGS = -10 V, VDD = -30 V PW = 5 s, duty < 1 % -1 -3 -10 -30 Drain Current ID (A) -100 td(off) tr td(on)
Repetitive Avalanche Energy EAR (mJ)
Maximum Avalanche Energy vs. Channel Temperature Derating 2.5 IAP = -5 A VDD = -25 V duty < 0.1 % Rg > 50
Switching Time t (ns)
2.0
1.5
1.0 0.5 0 25
50
75
100
125
150
Channel Temperature Tch (C) Switching Time Waveform Vout Monitor Vin 10% 90%
Switching Time Test Circuit Vin Monitor Rg D.U.T. RL V DD = -30 V Vout td(on)
Vin -10 V
90% 10% tr td(off)
90% 10% tf
Avalanche Test Circuit 1 2
Avalanche Waveform
2
V DS Monitor
L I AP Monitor
EAR =
L * I AP *
VDSS VDSS - V DD
V (BR)DSS I AP VDD ID V DS
Rg Vin -15 V
D. U. T
50 0 VDD
Rev.1.00, Oct.20.2003, page 12 of 15
HAT3018R, HAT3018RJ * In common
Power vs. Temperature Derating
Test Condition: When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) PW 10 s
4.0
Pch (W) Channel Dissipation
3.0
2.0
1 Dr ive
2
1.0
Op
iv Dr
er
e
at
Op
ion
er at ion
0
50 100 Case Temperature
150 Tc (C)
200
Rev.1.00, Oct.20.2003, page 13 of 15
HAT3018R, HAT3018RJ
Normalized Transient Thermal Impedance vs. Pulse Width (1 Drive Operation) 10
Normalized Transient Thermal Impedance s (t)
D=1 1
0.1
0.05
0.02
0.01
0.01
p ot uls e
ch - f(t) = s (t) x ch - f ch - f = 125C/W, Ta = 25C When using the glass epoxy board (FR4 40x40x1.6 mm)
PDM PW T
0.001
h 1s
D=
PW T
0.0001 10
100
1m
10 m
100 m
1
10
100
1000
10000
Pulse Width PW (S)
Normalized Transient Thermal Impedance vs. Pulse Width (2 Drive Operation) 10
Normalized Transient Thermal Impedance s (t)
1
D=1 0.5
0.2
0.1
0.1 0.05
0.02
0.01
0.01
uls e
ch - f(t) = s (t) x ch - f ch - f = 166C/W, Ta = 25C When using the glass epoxy board (FR4 40x40x1.6 mm)
PDM PW T
0.001
1s h
p ot
D=
PW T
0.0001 10
100
1m
10 m
100 m
1
10
100
1000
10000
Pulse Width PW (S)
Rev.1.00, Oct.20.2003, page 14 of 15
HAT3018R, HAT3018RJ
Package Dimensions
As of January, 2003
Unit: mm
4.90 5.3 Max 5 8
1
4
3.95
*0.22 0.03 0.20 0.03
1.75 Max
0.75 Max
6.10 - 0.30
+ 0.10
1.08 0 - 8
+ 0.67
0.14 - 0.04
+ 0.11
1.27
0.60 - 0.20
*0.42 0.08 0.40 0.06
0.15 0.25 M
*Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-8DA Conforms -- 0.085 g
Rev.1.00, Oct.20.2003, page 15 of 15
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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